View ALD_1208723.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
ALD SERIES
: PRELIMINARY
APPLICATIONS: * SONET, xDSL * SDH, CPE * STB
5.08 x 7.0 x 1.8mm
|||||||||||||||
FEATURES: * Based on a proprietary digital multiplier * 2.5V to 3.3V +/- 5% operation * Tri-State Output * Ceramic SMD, low profile package * Low Phase Jitter * 156.25MHz, 187.5MHz, and 212.5MHz applications
STANDARD SPECIFICATIONS:
PARAMETERS Frequency Range Operating Temperature Storage Temperature Overall Frequency Stability Supply Voltage (Vdd) Linearity Jitter (12KHz - 20MHz) Phase Noise 750 KHz to 800 MHz 0C to + 70C (see options) - 40C to + 85C 50 ppm max. (see options) 2.5V to 3.3 Vdc 5% 5% typ, 10% max. RMS phase jitter 3pS typ. < 5pS max. period jitter < 35pS peak to peak -109 dBc/Hz @ 1kHz Offset from 622.08MHz -110 dBc/Hz @ 10kHz Offset from 622.08MHz -109 dBc/Hz @ 100kHz Offset from 622.08MHz "1" (VIH > 0.7*VDD) or open: Oscillation/ "0" (VIH > 0.3*VDD) No Oscillation/Hi Z 80mA (Fo < 155.52MHz), 100mA (Fo < 155.52MHz) 45% min, 50% typical, 55% max. VDD -1.025V min, VDD -0.880V max. VDD -1.810V min, VDD -1.620V max. 1.5ns max, 0.6nSec typical 1.5ns max, 0.6nSec typical 1.6ns max, 1.2ns typical 45% min, 50% typical, 55% max 60mA max, 55mA typical. 45% min, 50% typical, 55% max 247mV min, 355mV typical, 454mV max -50mV min, 50mV max VOH = 1.6V max, 1.4V typical VOL = 0.9V min, 1.1V typical VOS = 1.125V min, 1.2V typical, 1.375V max VOS = 0mV min, 3mV typical, 25mV max 10A max, 1A typical 0.2ns min, 0.5ns typical, 0.7ns max 0.2ns min, 0.5ns typical, 0.7ns max
30332 Esperanza, Rancho Santa Margarita, California 92688 tel 949-546-8000 | fax 949-546-8001 | www.abracon.com
Tri-State Function PECL Supply Current (IDD) Symmetry (Duty Cycle) Output Logic High Output Logic Low Clock Rise time (tr) @ 20/80% Clock Fall time (tf) @ 80/20%
CMOS Output Clock Rise/ Fall Time [10%~90% VDD with 10pF load] Output Clock Duty Cycle [Measured @ 50% VDD] LVDS Supply Current (IDD) [Fout = 212.50MHz] Output Clock Duty Cycle @ 1.25V Output Differential Voltage (VOD) VDD Magnitude Change (VOD) Output High Voltage Output Low Voltage Offset Voltage [RL = 100] Offset Magnitude Voltage[RL = 100] Power-off Leakage (IOXD) [Vout=VDD or GND, VDD=0V] Differential Clock Rise Time (tr) [RL=100, CL=10pF] Differential Clock Fall Time (tf) [RL=100, CL=10pF]
ABRACON IS ISO 9001 / QS 9000 CERTIFIED
rev1.1-5/05
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
ALD SERIES
PIN ASSIGNMENTS:
PIN # 1 2 3 4 5 6 NAME Tri-state or VC Tri-state or NC GND Q Q VDD DESCRIPTION Tri-state or Voltage Control Tri-state or No Connect Ground PECL, LVDS, or CMOS Output Complimentary PECL,LVDS, or NC VDD Connection
: PRELIMINARY
5.08 x 7.0 x 1.8mm
|||||||||||||||
TRI-STATE PIN OPERATION:
OUTPUT TYPE PECL (P) LVDS & CMOS (L, C) PECL1 (P1) PIN 1 LOGIC LEVEL* 0 (Default) 1 0 1(Default) 0 1(Default) OUTPUT STATE Enabled Tri-state Tri-state Enabled Tri-state Enabled
*Connect to VDD from logic level "1", connect to ground for logic level "0".
MARKING:
- TUH - ALD ZYX (Frequency: T=First ""10" digit of frequency, U=First "unit" of frequency, H=First "tenth" of frequency, Ex: 100 for 10.0MHz) (Z: Month, A to L; Y: Year, 5 for 2005; X: Traceability Code)
OUTLINE DRAWING:
OPTIONS AND PART IDENTIFICATION (Left blank if standard):
ALD - Frequency - Temperature - Frequency Stability - Output - Packaging Temperature: D for -10C to +60C E for -20C to +70C F for -30C to +70C N for -30C to +85C L for -40C to +85C Stability options: R for 25 ppm K for 30 ppm H for 35 ppm Output options: P = PECL L = LVDS C = CMOS P1 = PECL1
Dimensions: inch (mm)
Tri-State option: A for Pin 1 = NC, Pin 2 = Tristate Packaging option: T for Tape and Reel (1,000pcs/reel)
ABRACON IS ISO 9001 / QS 9000 CERTIFIED
rev2.1-10/05
30332 Esperanza, Rancho Santa Margarita, California 92688 tel 949-546-8000 | fax 949-546-8001 | www.abracon.com

▲Up To Search▲

Price & Availability of ALD

	To Download ALD Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .